1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device having a multilayer interconnection structure.
2. Description of the Background Art
LSI semiconductor elements and liquid-crystal display panels have employed fine or miniaturized multilayer interconnection structures. FIGS. 12A, 13A, . . . 17A are plans showing layouts and particularly showing a first process of manufacturing a semiconductor device having a multilayer interconnection structure in the prior art. FIGS. 12B, 13B, . . . 17B are cross sections taken along line 100--100 in FIGS. 12A through 17A, respectively. Referring to FIGS. 12A and 12B through 17A and 17B, the first manufacturing process in the prior art will be described below.
As shown in FIGS. 12A and 12B, a sputtering method or the like is performed to form a lower interconnection layer 1 made of tungsten silicide.
Then, as shown in FIGS. 13A and 13B, a CVD method or the like is performed to form an interlayer insulating film 2 which covers lower interconnection layer 1 and is made of, e.g., a silicon oxide film.
Then, as shown in FIGS. 14A and 14B, a hole pattern (i.e., opening) 2a reaching lower interconnection layer 1 is formed at a predetermined region in interlayer insulating film 2.
Then, as shown in FIGS. 15A and 15B, processing is performed to form a conductive layer 3a made of a tungsten silicide film, which extends over the side surface of opening 2a and the upper surface of interlayer insulating film 2, and is in contact with a portion of lower interconnection layer 1 in opening 2a. Conductive film 3a is formed, e.g., by a sputtering method.
Then, as shown in FIGS. 16A and 16B, a resist pattern 15 is formed over a predetermined region of conductive layer 3a. A portion of resist pattern 15, which overlaps with lower interconnection layer 1, has a large width W which is determined taking an overlapping margin D into consideration.
After this state, an anisotropic etching is effected on conductive layer 3a at the lower level masked with resist pattern 15, and then resist pattern 15 is removed, so that upper interconnection layer 3 is formed shown in FIGS. 17A and 17B.
FIGS. 18A and 18B show upper interconnection layer 3 which is formed when resist pattern 15 shown in FIGS. 16A and 16B was shifted from the intended position. In resist pattern 15 shown in FIGS. 16A and 16B, the portion overlapping with lower interconnection layer 1 has the large width W which is determined taking the overlapping margin D into consideration. Therefore, even if resist pattern 15 was located at a shifted position during exposure, finally formed upper interconnection layer 3 is formed along the side surface of opening 2a as shown in FIGS. 18A and 18B, so that no disadvantage arises.
However, in accordance with recent increase in integration density of semiconductor devices, miniaturization of interconnection layers has been requested. Therefore, it is now required to reduce the width of upper interconnection layer 3 shown in FIGS. 17A and 17B.
FIGS. 19A and 20A are plans showing layouts and particularly showing a second manufacturing process of a semiconductor device in the prior art for coping with the above request, and FIGS. 19B and 20B are corresponding cross sections. Referring to FIGS. 19A and 19B as well as FIGS. 20A and 20B, the second manufacturing process in the prior art will be described below. First, a process similar to the conventional first manufacturing process shown in FIGS. 12A and 12B through 15A and 15B is performed to form a structure similar to that shown in FIGS. 15A and 15B. Then, as shown in FIGS. 19A and 19B, a resist pattern 5 is formed at a predetermined region on conductive layer 3a. For miniaturization, resist pattern 5 has a central portion narrower than that of resist pattern 15 shown in FIGS. 16A and 16B. Thus, resist pattern 5 shown in FIGS. 19A and 19B has a small and uniform width. Etching is effected on conductive layer 3a masked with resist pattern 5, and then resist pattern 5 is removed, so that upper interconnection layer 3 having a small uniform width shown in FIGS. 20A and 20B is formed.
The conventional second manufacturing process allowing miniaturization shown in FIGS. 19A, 19B, 20A and 20B suffers from the following problem. Referring to FIGS. 21A, 21B, 22A and 22B, the problem will be described below. As shown in FIGS. 21A and 21B, when resist pattern 5 was located at a shifted position during exposure, it is difficult to fill completely contact hole 2a because resist pattern 5 has a small width. More specifically, as shown in FIG. 21B, resist pattern 5 does not completely fill the concavity which is defined by conductive layer 3a located in opening 2a. If etching were effected on conductive layer 3a masked with resist pattern 5 thus formed, upper interconnection layer 3 and lower interconnection layer 1 would be partially etched as shown in FIG. 22B, and breakage of the interconnections would occur in the worst case. Therefore, it has been difficult to use the manufacturing method shown in FIGS. 19A, 19B, 20A and 20B, and one must use the manufacturing process shown in FIGS. 12A and 12B through FIGS. 17A and 17B which is not suitable to miniaturization. As a result, it is difficult to provide a manufacturing process suitable to miniaturization of elements in the prior art.